Как объявить входы и выходы, когда они противоположны для разных модулей процессора в verilog?

module alucontrol(iw,cntrl,Ra,Rb,Wa);
input [14:0]iw;
output reg [3:0]cntrl;
output reg [3:0]Ra;
output reg [3:0]Rb;
output reg [3:0]Wa;

always@(*)
begin
cntrl=iw[14:12];            
Ra=iw[11:8];
Rb=iw[7:4];
Wa=iw[3:0];
end

endmodule
////////////////////////////////////////////
module alumemory(Ra,Rb,Wa,A,B);
input wire [3:0]Ra,Rb,Wa;
output reg [3:0]A,B;

reg [3:0]  mem [0:15]; 
reg array[3:0][0:15];

always@(*)
begin
array[3:0][0]=4'b0100;
array[3:0][1]=4'b1001;
array[3:0][2]=4'b0110;
array[3:0][3]=4'b0010;
array[3:0][4]=4'b0100;
array[3:0][5]=4'b1101;
array[3:0][6]=4'b0100;
array[3:0][7]=4'b0001;
array[3:0][8]=4'b0000;
array[3:0][9]=4'b1111;
array[3:0][10]=4'b1000;
array[3:0][11]=4'b1001;
array[3:0][12]=4'b1000;
array[3:0][13]=4'b1011;
array[3:0][14]=4'b1100;
array[3:0][15]=4'b1010;
end

integer my_int1;
always@(1)
begin
my_int1=Ra;
A[3:0]=array[3:0][my_int1];
end 

integer my_int2;
always@(1)
begin
my_int2=Rb;
B[3:0]=array[3:0][my_int2];
end

integer my_int3;
always@(1)
begin
my_int3=Wa;
array[3:0][my_int3]=C[3:0];
end


endmodule
////////////////////////////////////
module Decoder(cntrl[3:0],adden, suben, mulen, diven, anden, oren, xoren, noten);
	input [3:0]cntrl;
	output adden, suben, mulen, diven, anden, oren, xoren, noten;
	assign adden=(~a&~b&~c),
			 suben=(~a&~b&c),
			 mulen=(~a&b&~c),
			 diven=(~a&b&c),
			 anden=(a&~b&~c),
			 oren=(a&~b&c),
			 xoren=(a&b&~c),
			 noten=(a&b&c);
endmodule
//////////////////////////////////////////////////
module alu_arith(input[3:0]A,
input adden, input suben,input mulen,input diven,input anden,input oren,input xoren,input noten,
input[3:0]B,
output reg [7:0]C
);
reg cntrlinp[7:0];
//wire[3:0]A;
//wire[3:0]B;
assign cntrlinp[0]=adden,
       cntrlinp[1]=suben,
        cntrlinp[2]=mulen,cntrlinp[3]=diven,cntrlinp[4]=anden,cntrlinp[5]=oren,cntrlinp[6]=xoren,cntrlinp[7]=noten;
always@(*)
begin
case(ctrlinp[7:0])
00000001:C=A+B;
00000010:C=A-B;
00000100:C=A*B;
00001000:C=A/B;
00010000:C=A&B;
00100000:C=A|B;
01000000:C=A^B;
10000000:C=~A;
default: C=8'b00000001;
endcase
end
	
endmodule

///////////////////////////////////////////////////////

module testbench;
reg[14:0]iw;
wire[7:0]C;

alucontrol a1(iw, cntrl,Ra,Rb,Wa);
alumemory a2(Ra,Rb,Wa,A,B);
alu_arith a3(A,B,C);
Decoder a4(cntrl,adden, suben, mulen, diven, anden, oren, xoren, noten);

initial begin
	$display("time\t A  B  cntrl  C");
    $monitor("%g\t %b %b %b %b",
    $time, A, B, cntrl, C);
	
	#0  C=8'b00000000;
		iw=15'b101000101011010;
	#5  iw=15'b001100110011001;
	#10 iw=15'b010101110101110;
	end
	
		
endmodule